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NOIL2SM1300A
LVDS Block
The LVDS block is positioned below the data block. It
receives a differential clock signal, transmits differential
data over the 12 data channels, and transmits a LVDS clock
signal and a synchronization signal over the clock and
synchronization channel.
A number of LVDS transmitter blocks are placed in
parallel to serve all data, clock, and synchronization output
channels. A high level overview is illustrated in the
following figure.
Serializer
LVDS
Transmitter
clock
Se rialize r<0 >
LVDS
Transmitter
<0>
Serializer <1>
LVDS
Transmitter
<1>
… Serializer <11>
LVDS
Transmitter
<11>
cloc kge nerato r
LVDS
Se rializer
LVDS
Transmitter
Synch
Receiver
Figure 8. LVDS Block ? High Level Overview
The function of this block is to take 10 bits of the protocol
block, serialize these bits, and converts them to an LVDS
standard (TIA/EIA 644A) compatible differential output
signal. The block must also provide a clock to the host, to
allow data recovery. This clock is an on-chip version of the
clock coming from the host.
Sequencer and Logic
The sequencer generates the complete internal timing of
the pixel array and the readout. The timing can be controlled
by the user through the SPI register settings. The sequencer
operates on the same clock as the data block. This is a
division by 10 of the input clock (internally divided).
Table 9 lists the internal registers. These registers are
discussed in detail in Detailed Description of Internal
Registers on page 15.
Table 9. INTERNAL REGISTERS
Block
MBS
(reserved)
LVDS clk
divider
Register Name
Fix1
Fix2
Fix3
Fix4
Fix5
lvdsmain
lvdspwd1
lvdspwd2
Address [6..0]
0
1
2
3
4
5
6
7
Field
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
[7:4]
[7:0]
[5:0]
Reset Value
0x00
0xFF
0x00
0x00
0x08
‘0110’
0
0x00
0
Description
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
lvds trim
clkadc phase
Power down channel 7:0
Power down channel 13:8
[6]
[7]
0
0
Power down all channels
lvds test mode
Fix6
8
[7:0]
0x00
Reserved, fixed value
AFE
afebias
afemode
9
10
[3:0]
[2:0]
‘1000’
‘111’
afe current biasing
vrefp, vrefm settings
[5:3]
[6]
‘000’
0
Pga settings
Power down AFE
afepwd1
11
[7:0]
0x00
Power down adc_channel_2x 7 to 0
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